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? january 2003 1/22 n cmos compatible input n on state open load detection n off state open load detection n shorted load protection n undervoltage and overvoltage shutdown n protection against loss of ground n very low stand-by current n reverse battery protection (*) description the vn920d-b5, VN920DSO are monolithic devices made by using stmicroelectronics vipower m0-3 technology, intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). active current limitation combined with thermal shutdown and automatic restart protect the device against overload. the device detects open load condition both is on and off state. output shorted to v cc is detected in the off state. device automatically turns off in case of ground pin disconnection. type r ds(on) i out v cc vn920d-b5 VN920DSO 18 m w 30 a 36 v block diagram undervoltage overtemperature v cc gnd input output overvoltage current limiter logic driver power clamp status v cc clamp on state openload off state openload and output shorted to v cc detection detection detection detection detection (*) see application schematic at page 8 p 2 pak so-16l order codes package tube t&r so-16l VN920DSO VN920DSO13tr p 2 pak vn920d-b5 vn920d-b513tr vn920d-b5 / VN920DSO high side driver
2/22 vn920d-b5 / VN920DSO absolute maximum rating connection diagram (top view) current and voltage conventions symbol parameter value unit p 2 pak so-16l v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a - i out reverse dc output current - 25 a i in dc input current +/- 10 ma i stat dc status current +/- 10 ma v esd electrostatic discharge (human body model: r=1.5k w; c=100pf) - input - current sense - output - v cc 4000 4000 5000 5000 v v v v e max maximum switching energy (l=0.25mh; r l =0 w ; v bat =13.5v; t jstart =150oc; i l =45a) 364 352 mj p tot power dissipation t c =25c 96.1 8.3 w t j junction operating temperature internally limited c t c case operating temperature - 40 to 150 c t stg storage temperature - 55 to 150 c v cc output output output output v cc output output v cc n.c. n.c. status input v cc gnd n.c. 1 8 9 16 so-16l input i s i in v in v cc status i stat v stat gnd v cc i out v out i gnd output 3 2 1 4 5 v cc gnd input status output p 2 pak
3/22 vn920d-b5 / VN920DSO thermal data (*) when mounted on a standard single-sided fr-4 board with 0.5cm 2 of cu (at least 35 m m thick). (**) when mounted on fr4 printed circuit board with 0.5cm 2 of cu (at least 35 m thick) connected to all v cc pins. electrical characteristics (8v 4/22 vn920d-b5 / VN920DSO 2 electrical characteristics (continued) status pin protections openload detection symbol parameter test conditions min typ max unit v stat status low output voltage i stat =1.6ma 0.5 v i lstat status leakage current normal operation v stat =5v 10 m a c stat status pin input capacitance normal operation v stat =5v 100 pf v scl status clamp voltage i stat =1ma i stat =-1ma 66.8 -0.7 8v v symbol parameter test conditions min typ max unit t tsd shut-down temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c t sdl status delay in overload condition t j >t tsd 20 m s i lim current limitation 5.5v v ol t dol(on) t j > t tsd v in v stat t sdl t sdl
5/22 vn920d-b5 / VN920DSO t t v out v in 80% 10% dv out /dt (on) t d(off) 90% dv out /dt (off) t d(on) switching time waveforms truth table conditions input output status normal operation l h l h h h current limitation l h h l x x h (t j < t tsd ) h (t j > t tsd ) l overtemperature l h l l h l undervoltage l h l l x x overvoltage l h l l h h output voltage > v ol l h h h l h output current < i ol l h l h h l
6/22 vn920d-b5 / VN920DSO iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 w 2 +25 v +50 v +75 v +100 v 0.2 ms 10 w 3a -25 v -50 v -100 v -150 v 0.1 m s 50 w 3b +25 v +50 v +75 v +100 v 0.1 m s 50 w 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 w 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 w iso t/r 7637/1 test pulse test levels results iiiiiiiv 1cccc 2cccc 3acccc 3bcccc 4cccc 5ceee electrical transient requirements on v cc pin class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
7/22 vn920d-b5 / VN920DSO open load without external pull-up status input normal operation undervoltage v cc v usd v usdhyst input overvoltage v cc v cc >v ov status input status status input status input open load with external pull-up undefined figure1: waveforms load voltage v cc v ol v ol
8/22 vn920d-b5 / VN920DSO gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / (i s(on)max ). 2) r gnd 3 (- v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the of the devices datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggest to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k w) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. m c i/os protection: if a ground protection network is used and negative transient are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the m c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of m c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of m c i/os. -v ccpeak /i latchup r prot (v oh m c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 3 20ma; v oh m c 3 4.5v 5k w r prot 65k w . recommended r prot value is 10k w. 1 application schematic v cc gnd output d gnd r gnd d ld m c +5v r prot v gnd status input +5v r prot
9/22 vn920d-b5 / VN920DSO 1 1 high level input current input clamp voltage off state output current -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 iih (ua) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vicl (v) iin=1ma input high level -50 -25 0 25 50 75 100 125 150 175 tc (c) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v) input hysteresis voltage input low level -50 -25 0 25 50 75 100 125 150 175 tc (c) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 1 2 3 4 5 6 7 8 9 il(off1) (ua)
10/22 vn920d-b5 / VN920DSO overvoltage shutdown turn-on voltage slope turn-off voltage slope i lim vs. t case -50 -25 0 25 50 75 100 125 150 175 tc (c) 30 32 34 36 38 40 42 44 46 48 50 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc (oc) 250 300 350 400 450 500 550 600 650 700 dvout/dt(on) (v/ms) vcc=13v rl=1.3ohm -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 50 100 150 200 250 300 350 400 450 500 550 dvout/dt(off) (v/ms) vcc=13v rl=1.3ohm on state resistance vs. t case on state resistance vs. v cc -50 -25 0 25 50 75 100 125 150 175 tc (o c) 0 10 20 30 40 50 60 70 80 90 100 ilim (a) vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 0 5 10 15 20 25 30 35 40 45 50 ron (mohm) iout=10a vcc=8v; 36v 5 10152025303540 vcc (v) 0 5 10 15 20 25 30 35 40 45 50 ron (mohm) iout=10a tc=150oc tc=25oc tc= -40oc
11/22 vn920d-b5 / VN920DSO status leakage current status low output voltage status clamp voltage -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 ilstat( m a) vstat=5v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 vstat (v) istat=1.6ma -50 -25 0 25 50 75 100 125 150 175 tc (oc) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vscl (v) istat=1ma
12/22 vn920d-b5 / VN920DSO p 2 pak maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 w in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. v in , i l t demagnetization demagnetization demagnetization 1 10 100 0.01 0.1 1 10 100 l(mh) i lmax (a) a b c
13/22 vn920d-b5 / VN920DSO so-16l maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 w in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. v in , i l t demagnetization demagnetization demagnetization 1 10 100 0.01 0.1 1 10 100 l(mh) i lmax (a) a b c
14/22 vn920d-b5 / VN920DSO p 2 pak pc board r thj-amb vs. pcb copper area in open box free air condition p 2 pak thermal data layout condition of r th and z th measurements (pcb fr4 area= 60mm x 60mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: 0.97cm 2 , 8cm 2 ). 30 35 40 45 50 55 0246810 pcb cu heatsink area (cm^2) rthj_amb (c/w) tj-tamb=50c
15/22 vn920d-b5 / VN920DSO so-16l pc board r thj-amb vs. pcb copper area in open box free air condition so-16l thermal data layout condition of r th and z th measurements (pcb fr4 area= 41mm x 48mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: 0.5cm 2 , 6cm 2 ). 40 45 50 55 60 65 70 01234567 pcb cu heatsink area (cm^2) rth j-amb (c/w)
16/22 vn920d-b5 / VN920DSO thermal fitting model of a single channel hsd in so-16l pulse calculation formula thermal parameter area/island (cm 2 ) footprint 6 r1 (c/w) 0.02 r2 (c/w) 0.1 r3 ( c/w) 2.2 r4 (c/w) 12 r5 (c/w) 15 r6 (c/w) 35 20 c1 (w.s/c) 0.0015 c2 (w.s/c) 7.00e-03 c3 (w.s/c) 1.50e-02 c4 (w.s/c) 0.14 c5 (w.s/c) 1 c6 (w.s/c) 5 8 z th d r th d z thtp 1 d C () + = where d t p t = so-16l thermal impedance junction ambient single pulse 0.01 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) footprint 6 cm 2 t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj
17/22 vn920d-b5 / VN920DSO thermal fitting model of a single channel hsd in p 2 pak pulse calculation formula thermal parameter area/island (cm 2 ) footprint 6 r1 (c/w) 0.02 r2 (c/w) 0.1 r3 (c/w) 0.22 r4 (c/w) 4 r5 (c/w) 9 r6 (c/w) 37 22 c1 (w.s/c) 0.0015 c2 (w.s/c) 0.007 c3 (w.s/c) 0.015 c4 (w.s/c) 0.4 c5 (w.s/c) 2 c6 (w.s/c) 3 5 z th d r th d z thtp 1 d C () + = where d t p t = p 2 pak thermal impedance junction ambient single pulse t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj 0.01 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) footprint 6 cm 2
18/22 vn920d-b5 / VN920DSO dim. mm. min. typ max. a4.30 4.80 a1 2.40 2.80 a2 0.03 0.23 b0.80 1.05 c0.45 0.60 c2 1.17 1.37 d8.95 9.35 d2 8.00 e 10.00 10.40 e1 8.50 e3.20 3.60 e1 6.60 7.00 l 13.70 14.50 l2 1.25 1.40 l3 0.90 1.70 l5 1.55 2.40 r 0.40 v2 0o 8o package weight 1.40 gr (typ) p010r p 2 pak mechanical data
19/22 vn920d-b5 / VN920DSO 1 1 1 1 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45 (typ.) d 10.1 10.5 0.397 0.413 e 10.0 10.65 0.393 0.419 e 1.27 0.050 e3 8.89 0.350 f 7.4 7.6 0.291 0.300 l 0.5 1.27 0.020 0.050 m 0.75 0.029 s8 (max.) so-16l mechanical data
20/22 vn920d-b5 / VN920DSO 1 all dimensions are in mm. base q.ty 50 bulk q.ty 1000 tube length ( 0.5) 532 a 18 b 33.1 c ( 0.1) 1 tape and reel shipment (suffix 13tr) all dimensions are in mm. base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 60 t (max) 30.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 16 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 11.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed reel dimensions c b a 9.4 16.15 4.6 10.8 0.6 1.1 7.9 p 2 pak tube shipment (no suffix ) p 2 pak suggested pad layout all dimensions are in mm.
21/22 vn920d-b5 / VN920DSO so-16l tube shipment (no suffix) 1 all dimensions are in mm. base q.ty 50 bulk q.ty 1000 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 tape and reel shipment (suffix 13tr) base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 16.4 n (min) 60 t (max) 22.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 16 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 7.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed a c b reel dimensions
22/22 vn920d-b5 / VN920DSO information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy- all rights reserved. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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